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PanaX NEO (Debugging Environment)

Feature of PanaX NEO
PanaX NEO is a new debugging environment designed to take the place of previous on-board debugging environments.
Compared to previous on-board debugging environments, PanaX NEO incorporates expandability for the future along with enhancements to the functionality required for software debugging of upcoming microcomputers and system LSIs.
See the following features.
  • Standard host computer connectivity is via USB 1.1/2.0 and Ethernet 10Base-T/100Base-TX.
  • Extending functionality
    - Each unit is stack-structured, which enables to add newly developed units (e.g. trace unit with large capacity, ROM emulator) to extend functionality.
  • PanaX NEO Image
  • High-speed tracing
    - Maximum acquisition clock frequency is up to 200MHz.
    - Tracing on both edges of the clock is supported.
    - Trace memory can record results of 512 kframes.
    - Improved reliability with differential transmission.
  • Interface voltage
    - JTAG: 1.8V to 3.3V
    - DWire32A: 2.5V to 5.0V
    - Trace: 1.8V to 3.3V
  • Redesigned target connecting adapter
    - Improving reliability by detecting version mismatch or misuse of connected adapters.
    - Providing standard cables (about 45cm) and long cables (about 120cm) as target connection cable.
  • Adoption of high-capacity FPGAs
    - Supporting LSI including multi-core debugging and performance evaluation function.
Composition of PanaX NEO
PanaX NEO
PX-ODBHUT: Base Unit
- Host Computer IF
- CPU for controlling the units
PX-ODBSUT: Serial Communication Unit
- Debugging target device communication control block
- DWire32A/JTAG
PX-ODBDUT: Trace Unit
- Trace control block

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